Galois field multiplication system and method

ABSTRACT

A present invention Galois field multiplier system and method utilize lookup tables to generate one partial product term and one feedback term in one clock cycle. In one embodiment, a Galois field multiplier system includes a plurality of shift registers, a plurality of exclusive OR components, a partial product lookup table, and a feedback table lookup table. The plurality of shift registers perform shift multiplication operation and are coupled to the plurality of shift registers that perform addition operations. The partial product lookup table and feedback lookup tables are selectively coupled to the exclusive OR components and values from the partial product lookup table and feedback lookup tables are fed into the selectively coupled exclusive OR components. Coefficients of the partial product term and feedback term are utilized as indexes to the partial product lookup table and feedback lookup table respectively.

FIELD OF THE INVENTION

This invention relates to the field of computational systems. Inparticular, the present invention relates to a Galois fieldmultiplication system and method.

BACKGROUND OF THE INVENTION

Electronic systems and circuits have made a significant contributiontowards the advancement of modern society and are utilized in a numberof applications to achieve advantageous results. Numerous electronictechnologies such as digital computers, calculators, audio devices,video equipment, and telephone systems facilitate increased productivityand cost reductions in analyzing and communicating data, ideas andtrends in most areas of business, science, education and entertainment.These results are often provided by systems that perform complicatedcomputational operations, including operations associated with codingand cryptography techniques utilizing Galois fields. Many coding andcryptography applications require the operations to be completed quicklyand slow results can have adverse impacts on performance. However,traditional Galois field computation approaches often involve arelatively significant amount of resources and/or a large number ofcomputation iterations that require a relatively long time to complete.

As various information processing systems advance and proliferate,reliable and efficient information communication and/or storage systemsare becoming more important and often critical. Emerging large-scaleand/or fast systems (e.g., storage devices, data networks, etc.) oftenrequire effective and dependable handling of vast amounts ofinformation. Traditional systems often utilize Galois fieldmultiplication and division to facilitate accurate and dependableexchange, processing and retention of information in a variety ofapplications. For example, Galois field computations are often used toensure information is secure and/or an accurately reproduced.

Reliably “reproducing” data without errors (e.g., introduced by a signal“corrupted” during communication) is one typical major concern in boththe communication and storage of information. Error detection andcorrection schemes typically involve encoding/decoding information“messages”. For example, a message is typically divided into blocks of kinformation bits each with a total of 2^(k) different possible messages.An encoder transforms each message into an n-tuple vector of discretesymbols called a code word or code vector. Code words and/or encryptedmessages are often encoded and decoded utilizing Galois fieldmanipulation. For example, codewords of cyclic codes are convenientlyrepresented as Galois field polynomials that are encoded and decodedusing multiplication and division of the Galois field representation.

Galois field multiplication and division can also be utilized incryptography operations by encoding messages to permit securecommunication over an otherwise insecure communication channel.Cryptography systems usually involve manipulations of a message inaccordance with a “key” and encryption/decryption rules. Traditionally,keys are utilized in both symmetric cryptographic system (e.g., based ona secret “key”) and asymmetric cryptographic systems (e.g., based upon apublic-private key pair). The underlying operations involved in thesecryptography systems often involve Galois field multiplication anddivision of the messages and keys to encrypt/decrypt cyphertext.

Traditional Galois field GF(2^(m)) multiplication and divisionapproaches often utilize single bitwise serial or parallel operations.Traditional parallel GF(2^(m)) multipliers typically generate n partialproducts and n feedback terms each n bits wide. Then an exclusive OR(XOR) of the n partial products and n feedback terms is performed to geta single final product. Bit parallel multipliers generally provideresults in one clock cycle (output bits are calculated in one clockcycle) and involve significant hardware (e.g., silicon area)requirements. The significant hardware requirements of bit parallelmultipliers often make them impractical for a number of large degreeapplications (e.g., a 2¹²⁸ multiplier for authentication in CPS GCMmode). Serial bit multipliers typically require less hardware and areusually well suited for normal basis representation allowing efficientexpontentiation.

While serial bit multipliers typically require less hardware, serial bitmultipliers usually require multiple clock cycles to provide a finaloutput. In conventional GF(2^(m)) serial approaches, a single bit isusually entered for each iteration (e.g., one output bit is calculatedper clock cycle). For example, in a typical traditional serialmultiplier approach one bit of a multiplier generates one partialproduct. Since the inputs (e.g., multiplier, quotient, etc) usually havea rather large number of bits, conventional approaches produce arelatively large number of partial products that require a significantnumber of XOR iterations, which can take a relatively significant amountof time to complete (e.g., due to large iteration delays).

SUMMARY

A Galois field multiplier system and method for reducing exclusive ORiterations in Galois field multiplication are presented. A presentinvention Galois field multiplier system and method utilize lookuptables to facilitate simplified and expedited Galois fieldmultiplication. The lookup tables permit the use of multiple bits of amultiplier to generate one partial product term and one feedback term inone clock cycle. In one embodiment, a Galois field multiplier systemincludes a plurality of shift registers, a plurality of exclusive ORcomponents, a partial product lookup table, and a feedback table lookuptable. The plurality of shift registers perform shift multiplicationoperations. The plurality of exclusive OR components are coupled to theplurality of shift registers and perform addition operations. Thepartial product lookup table is selectively coupled to the exclusive ORcomponents and values from the partial product lookup table are fed intothe selectively coupled exclusive OR components. Similarly, the feedbacktable lookup table is selectively coupled to the exclusive OR componentsand values from the feedback lookup table are fed into the selectivelycoupled exclusive OR components. The coefficients of the partial productterm and feedback term are utilized as indexes to the partial productlookup table and feedback lookup table respectively.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a Galois field multiplier system inaccordance with one embodiment of the present invention.

FIG. 2 is a block diagram of an exemplary partial product lookup tablesegment in accordance with one embodiment of the present invention.

FIG. 3 is a block diagram of an exemplary feedback selection inputcomponent in accordance with one embodiment of the present invention.

FIG. 4 is a flow chart of a Galois field multiplier method in accordancewith one embodiment of the present invention.

FIG. 5 is a flow chart of a finite field lookup table method inaccordance with one embodiment of the present invention.

DETAILED DESCRIPTION

Reference will now be made in detail to the preferred embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. While the invention will be described in conjunction with thepreferred embodiments, it will be understood that they are not intendedto limit the invention to these embodiments. On the contrary, theinvention is intended to cover alternatives, modifications andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims. Furthermore, in thefollowing detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be obvious toone ordinarily skilled in the art that the present invention may bepracticed without these specific details. In other instances, well knownmethods, procedures, components, and circuits have not been described indetail as not to unnecessarily obscure aspects of the current invention.

In one embodiment, a present invention Galois field multiplier systemand method utilizes multiple coefficient bits of a partial product termand feedback term as indexes to a partial product term lookup table anda feedback term lookup table respectively. The partial product termlookup table and the feedback term lookup table return partial productvalues and feedback values for use in Galois field multiplicationoperations. The lookup tables permit the use of multiple bits of amultiplier to generate one partial product term and one feedback term inone clock cycle.

In one exemplary implementation, a Galois Field GF(2^(n)) multiplier instandard basis is used in which:${A = {\sum\limits_{i = 0}^{n - 1}\quad{a_{i}\alpha^{i}}}},{B = {\sum\limits_{i = 0}^{n - 1}\quad{b_{i}\alpha^{i}}}},{{f(x)} = {x^{n} + {\sum\limits_{i = 0}^{n - 1}\quad{g_{i}x^{i}}}}},{{g(x)} = {\sum\limits_{i = 0}^{n - 1}\quad{g_{i}x^{i}}}}$for $C = {\sum\limits_{i = 0}^{n - 1}\quad{C_{i}\alpha^{i}}}$where C is the product of A and B. For example, the operation for C canbe written as follows: $\begin{matrix}{C = {{{AB}{mod}}\quad{f(x)}}} \\{= {\left( {{Ab}_{0}{mod}\quad{f(x)}} \right) + \left( {{Ab}_{1}\alpha\quad{mod}\quad{f(x)}} \right) + \left( {{Ab}_{2}\alpha^{2}{mod}\quad{f(x)}} \right) + \ldots + \left( {{Ab}_{n - 1}\alpha^{n - 1}{mod}\quad{f(x)}} \right)}} \\{= {{b_{0}A} + {b_{1}\left( {A\quad\alpha\quad{mod}\quad{f(x)}} \right)} + {b_{2}\left( {A\quad\alpha^{2}{mod}\quad{f(x)}} \right)} + \ldots + {b_{n - 1}\left( {{A\alpha}^{n - 1}{mod}\quad{f(x)}} \right)}}}\end{matrix}$in a least significant bit (LSB) first implementation. Alternatively,the equation for C can be written as: $\begin{matrix}{C = {{AB}\quad{mod}\quad{f(x)}}} \\{= {{\left( {{\ldots\left( {{{Ab}_{n - 1}\alpha} + {Ab}_{n - 2}} \right)}{\alpha++}{Ab}_{1}} \right)\alpha} + {{Ab}_{0}{mod}\quad{f(x)}}}}\end{matrix}$in a most significant bit (MSB) first implementation. Using a MSB firstexample, for step or iteration “k”, where k is greater than zero andless than n+1 (e.g., 0<k<n+1)then:C(k)=C(k−1)α+A b _(n−k) mod f(x)for each C(k).

In one embodiment, the operations for determining C(k) include shiftoperations (e.g., a left shift by one), feedback operations and partialproduct operations. When C(k), A and g are treated as n-element arraysand using the definition:A[n−1:0] α mod f(x)={A[n−2:0],1′b 0}+(A[n−1] g)the operations for determining C(k) can be expressed as: $\begin{matrix}{{C(k)} = {\left\{ {{{C\left( {k - 1} \right)}\left\lbrack {n - {2\text{:}0}} \right\rbrack},{1^{\prime}{b0}}} \right\} + \left( {{{C\left( {k - 1} \right)}\left\lbrack {n - 1} \right\rbrack}g} \right) + {Ab}_{n - k}}} \\{= {\left\{ {{{C\left( {k - 1} \right)}\left\lbrack {n - {2\text{:}0}} \right\rbrack},{1^{\prime}{b0}}} \right\} + {{FB}(k)} + {{PP}\left( {n - k} \right)}}}\end{matrix}$where PP (n−k) is a partial product term and FB(k) is a feedback term.

In one embodiment, more than one bit is utilized to generate one partialproduct term for PP(n−k) and the total number partial products thatwould otherwise be performed is reduced, which in turn reduces thenumber of partial product XOR iterations that would otherwise beperformed. Similarly, more than one bit can be utilized to generate onefeedback term for FB(k). Again, the total number of feedback XORiterations that would otherwise be performed can be reduced. Multiplebits of the partial product PP(n−k) coefficient are utilized to generateone partial product term and multiple bits of the feedback FB(k)coefficient are utilized to generate one feedback term.

In one exemplary implementation, two bits are utilized to generate onepartial product term PP(n−k) and one feed back term FB(k). Theoperations for performing a Galois field multiplication using two bitsto generate the partial product term PP(n−k) and one feedback term FB(k)can be expressed as: $\begin{matrix}{{C\left( {k + 1} \right)} = {{{C\left( {k + 1} \right)}\left\lbrack {n - {1\text{:}0}} \right\rbrack} = {\left\{ {{{C(k)}\left\lbrack {n - {2\text{:}0}} \right\rbrack},{1^{\prime}{b0}}} \right\} + \left( {{{C(k)}\left\lbrack {n - 1} \right\rbrack}g} \right) + {Ab}_{n - k - 1}}}} \\{\left. {{= \left\{ {\left\{ {{{C\left( {k - 1} \right)}\left\lbrack {n - {3\text{:}0}} \right\rbrack},{1^{\prime}{b0}}} \right\} + \left( {{{C\left( {k - 1} \right)}\left\lbrack {n - 1} \right\rbrack}{g\left\lbrack {n - {2\text{:}0}} \right\rbrack}} \right) + {{A\left\lbrack {n - {2\text{:}0}} \right\rbrack}b_{n - k}}} \right\}},{1^{\prime}{b0}}} \right\} + \left( {{{C(k)}\left\lbrack {n - 1} \right\rbrack}g} \right) + {Ab}_{n - k - 1}} \\{= {\left\{ {{{C\left( {k - 1} \right)}\left\lbrack {n - {3\text{:}0}} \right\rbrack},{2^{\prime}{b00}}} \right\} +}}\end{matrix}$C(k−1)[n−1] {g[n−2:0], 1′b0}+C(k)[n−1] g+b _(n−k) {A[n−2:0], 1′b0}+b_(n−k−1) AThis can be rewritten as:C(k+1)={C(k−1)[n−3:0], 2′b00}+PP*[n−k]+FB*(k)with partial product term PP*[n−k] and feedback term FB*(k). The partialproduct operations can be expressed as:PP*[n−k]=b _(n−k) {A[n−2:0], 1′b0}+b _(n−k−1) Awith partial product term PP*[n−k] and feedback term FB*(k). Thefeedback operations can be expressed as: $\begin{matrix}{{{FB}^{*}(k)} = {{{{C\left( {k - 1} \right)}\left\lbrack {n - 1} \right\rbrack}\left\{ {{g\left\lbrack {n - {2\text{:}0}} \right\rbrack},{1^{\prime}{b0}}} \right\}} + {{{C(k)}\left\lbrack {n - 1} \right\rbrack}g}}} \\{= {{{{C\left( {k - 1} \right)}\left\lbrack {n - 1} \right\rbrack}\left\{ {{g\left\lbrack {n - {2\text{:}0}} \right\rbrack},{1^{\prime}{b0}}} \right\}} + {\left( {{{C\left( {k - 1} \right)}\left\lbrack {n - 2} \right\rbrack} + {{{C\left( {k - 1} \right)}\left\lbrack {n - 1} \right\rbrack}{g\left\lbrack {n - 1} \right\rbrack}} + {{A\left\lbrack {n - 1} \right\rbrack}{b\left\lbrack {n - k} \right\rbrack}}} \right)g}}}\end{matrix}$wherein C(k−1)[n−1] and C(k−1)[n−2]+C(k−1)[n−1]g[n−1]+An−1]b[n−k] arecoefficients of the feedback term. The coefficients of the partialproduct term and feedback term are utilized to generate one partialproduct term for PP(n−k) and one feed back for term FB(k).

In the present implementation, the partial product term is defined bytwo bits. The first partial product term PP(n−k) coefficient bit isdefined as:PP(n−k) first bit=b_(n−k)and the second partial product term PP(n−k) coefficient bit is definedas:PP(n−k) second bit=b _(n−k−1)wherein the first and second partial product term bits are coefficientsof the partial product term. The first feedback term FB(k) bit isdefined as:FB(k) first bit=C(k−1)[n−1]and the second partial product term PP(n−k) bit is defined as:FB(k) bit=(C(k−1)[n−2]+C(k−1)[n−1]g[n−1]+A[n−1]b[n−k])wherein the first and second feedback term bits are coefficients of thefeedback term.

FIG. 1 is a block diagram of Galois field multiplier system 100 inaccordance with one embodiment of the present invention. Galois fieldmultiplier system 100 includes shift registers 110 through 112,exclusive OR gates 121 through 124, feedback lookup table 191 andpartial product lookup table 192. The XOR gates 121 through 124 aresequentially coupled to interleaved respective shift registers 110through 112. The XOR gates 121 through 124 are also coupled to feedbacklookup table 191 and partial product lookup table 192. Feedback lookuptable 191 is coupled to feedback selection input 181. Partial productlookup table 192 is coupled to partial product selection input 130. TheXOR gate 121 forwards output 141.

The components of Galois field multiplier system 100 cooperativelyoperate to perform Galois field multiplication operations. Shiftregisters 110 through 112 perform shift “multiplication” operations.Exclusive OR components 121 through 124 perform logical exclusive OR“addition” operations. Partial product lookup table 192 forwards partialproduct values into the selectively coupled exclusive OR components 121through 124 in accordance with information from partial productselection input 130. Feedback lookup table 191 forwards feedback valuesinto the selectively coupled exclusive OR components 121 through 124 inaccordance with selection information from feedback selection input 181.

In one embodiment of the present invention, the coefficients of apartial product term are utilized as indexes to partial product lookuptable 192 and coefficients of a feedback term are utilized as indexes tofeedback lookup table 191. For example, a first partial productcoefficient 131 (e.g., b_(n−1)) and a second partial product coefficient132 (b_(n−i−1)) are utilized as indexes to partial product lookup table192. First feedback coefficient 182 (e.g., C(k−1)[n−1]) and secondfeedback coefficient 183 (e.g.,C(k−1)[n−2]+C(k−1)[n−1]g[n−1]+A[n−1]b[n−k]) are utilized as indexes tofeedback lookup table 191.

In one embodiment, a value field of the partial product lookup table isthe sum of partial products from non-zero partial product index bits anda value field of the feedback lookup table is the sum of feedback termsfrom non-zero feedback index bits. In one exemplary implementation, theindex address of the feedback table is calculated by a look aheadmethod. It is appreciated that a present invention lookup tables canhave a variety of configurations and implementations. In one embodimentof the present invention, lookup tables include multiplexers thatforward an output based upon the coefficient bits of a Galois fieldpolynomial term. For example, partial product lookup table component 192includes partial product multiplexers 151 through 154 and feedbacklookup table component 191 includes feedback multiplexers 171 through174. Partial product multiplexers 151 through 154 and feedbackmultiplexers 171 through 174 are coupled to exclusive OR gates 121through 123 respectively. Partial product multiplexers 151 through 154are also coupled to partial product selection input 130. Feedbackmultiplexers 171 through 174 are coupled to feedback selection input181. Partial product multiplexers 151 through 154 forward a partialproduct term value based upon partial product selection input 130.Feedback multiplexers 171 through 174 forward a feedback term valuebased upon feedback selection input 181.

In one embodiment of the present invention, partial product multiplexerconfigurations are dependent on the number of multiple bits that areutilized as coefficient inputs. FIG. 2 is a block diagram of anexemplary partial product lookup table segment 200 in accordance withone embodiment of the present invention. Partial product lookup tablesegment 200 includes partial product multiplexer 221 (e.g., similar topartial product multiplexers 151 through 154) coupled to inputs firstpartial product value 211, second partial product value 212, thirdpartial product values 213, and for the partial product value 214.Partial product multiplexer 221 forwards one of the inputs as the finalpartial product value 231 based upon partial product selection input 251(e.g., similar to partial product selection input 130). The partialproduct values can be calculated on the fly from input 205. For example,given input Ab, first partial product value 211 can be set to 0000,second partial product value 212 is set equal to A, and third partialproduct value 213 is set equal to A left shifted once. Forth partialproduct value 214 is set equal to A exclusive ORed with the value of Aleft shifted once.

FIG. 3 is a block diagram of an exemplary feedback coefficientdetermination component 300 in accordance with one embodiment of thepresent invention. In one exemplary implementation, feedback coefficientdetermination component 300 is utilized to determine (e.g., on the fly)a feedback coefficient for utilization as an index value to a feedbacklookup table. Feedback coefficient determination component 300 includesa first logical AND gate 321 and a second logical AND gate 322 coupledto logical XOR gate 331. The first coefficient determination input 311(e.g., C(k−1){n−2)), the outputs of first logical AND gate 321 and asecond logical AND gate 322 are coupled to logical XOR gate 331. Secondcoefficient determination input (e.g., C(k−1[n−1]) and third coefficientdetermination input 312 (e.g. g[n−1]) are coupled to the input of firstlogical AND gate 321. Forth coefficient determination input 314 (e.g.,A[n−1]) and fifth coefficient determination input 315 (e.g., b[n−k]) arecoupled to the input of second logical AND gate 322.

FIG. 4 is a flow chart of Galois field multiplier method 400 inaccordance with one embodiment of the present invention. Fieldmultiplier method 400 facilitates reduction of XOR iterations in Galoisfield multiplication operations. Field multiplier method 400 can beutilized with irreducible polynomials operations that are fixed orprogrammable.

In step 410 a lookup table is utilized to provide resulting coefficientvalues of polynomial terms. In one embodiment, the resulting coefficientvalues are resulting partial product coefficient values and resultingfeedback coefficient values. Multiple bits of a multiplier can beutilized as an index to the lookup table to generate one term (e.g., onepartial product term, one feedback term, etc.). In one exemplaryimplementation the term is generated in one clock cycle.

In step 420, an exclusive OR operation is performed on the resultingcoefficient values. In one embodiment of the present invention, theexclusive OR functions as a Galois field addition operation. Byutilizing the coefficient values from the lookup table of step 410, lessXOR operation iterations are performed than would otherwise be required.

In step 430, the results of the exclusive OR operation are shifted. Inone exemplary implementation the XOR operation results are shifted tothe left and the shifting functions as a Galois field multiplication.

The present invention can be implemented in a variety of systems (e.g.,computers, data processing systems, communication networks) and/ordiverse applications. For example, a present invention system and/ormethod can be implemented in a variety of storage devices (e.g., randomaccess memories, hard drive memories, flash memories, etc.) andcommunication equipment (e.g., routers, switches, etc.). A presentinvention system and/or method can be utilized to perform Galois fieldmultiplication and/or division associated with checking for errors ininformation (e.g. ECC encoding/decoding, etc.). A present inventionsystem and/or method can also be utilized to facilitate security schemesand/or message authentication in a variety of applications. For example,communication of confidential information (e.g., information associatedwith financial transactions, national security, etc) over a network(e.g., over the Internet). It is appreciated that a present inventionsystem and/or method can be implemented in a variety of cryptographyand/or encoding implementations. For example, Galois field multipliersystem 100 can be utilized to produce a codeword, a syndrome,cyphertext, etc. It is also appreciated that the present invention canbe implemented in hardware, software, firmware and/or combinationsthereof. For example, instructions for causing a processor to performGalois field multiplier method 400 can be stored on a computer readablemedium and executed by a processing system.

FIG. 5 is a flow chart of a finite field lookup table method 500, inaccordance with one embodiment of the present invention.

In step 510, create a finite field lookup table. In one embodiment, thefinite field lookup table is a partial product lookup table (e.g.,partial product lookup table 192). The finite field lookup table is afeedback lookup table (e.g., feedback lookup table 191. In one exemplaryimplementation the finite field lookup table maps finite field lookuptable values with indexes associated with multiplier coefficients.

In step 520, identify a multiplier coefficient as an index to the finitefield lookup table. In one embodiment of the present invention, a Galoisfield multiplication expression is parsed and coefficient values areextracted. For example, partial product coefficient values (e.g.,b_(n−k), b_(n−k−1)) are extracted. Feedback coefficient values (e.g.C(k−1)[n−1] and C(k)[n−1]) are extracted.

In step 530, the identified multiplier coefficient is utilized to returna value from the finite field lookup table.

Thus, the present invention is a system and method that facilitatesexpedited Galois field multiplication results. A present inventionGalois field multiplication system and method provides results fasterthan a traditional serial bit implementation without requiring thesignificant hardware resources (e.g., in terms of silicon area) oftraditional parallel multipliers. The lookup tables permit the use ofmultiple bits of a multiplier to generate one partial product term andone feedback term in one clock cycle.

The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed, and obviously manymodifications and variations are possible in light of the aboveteaching. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical application,to thereby enable others skilled in the art to best utilize theinvention and various embodiments with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the invention be defined by the Claims appended hereto and theirequivalents.

1. A Galois field multiplier system comprising: a plurality of shiftregisters for performing shift multiplication operations; a plurality ofexclusive OR components coupled to said plurality of shift registers,said plurality of exclusive OR components for performing additionoperations; and a partial product lookup table selectively coupled tosaid exclusive OR components, wherein values from said partial productlookup table are fed into said selectively coupled exclusive ORcomponents.
 2. The Galois field multiplier system of claim 1 whereincoefficients of a partial product term are utilized as indexes to saidpartial product lookup table.
 3. The Galois field multiplier system ofclaim 1 further comprising a feedback table lookup table selectivelycoupled to said exclusive OR components, wherein values from saidfeedback lookup table are fed into said selectively coupled exclusive ORcomponents.
 4. The Galois field multiplier system of claim 3 whereincoefficients of a feedback term are utilized as indexes to said feedbacklookup table.
 5. The Galois field multiplier system of claim 1 whereinGalois field multiplier system produces a codeword.
 6. The Galois fieldmultiplier system of claim 1 wherein Galois field multiplier systemproduces a syndrome.
 7. The Galois field multiplier system of claim 1wherein a value field of said partial product lookup table is the sum ofpartial products from non-zero index bits.
 8. The Galois fieldmultiplier system of claim 1 wherein a value field of said feedbacklookup table is the sum of feedback terms from non-zero index bits. 9.The Galois field multiplier system of claim 1 wherein the index addressof said feedback table is calculated by a look ahead method.
 10. TheGalois field multiplier method comprising: utilizing a lookup table toprovide resulting coefficient values of polynomial terms; performing anexclusive OR operation on said resulting coefficient values; andshifting results of said exclusive OR operation.
 11. The Galois fieldmultiplier method of claim 10 wherein said resulting coefficient valuesare resulting partial product coefficient values.
 12. The Galois fieldmultiplier method of claim 10 wherein said resulting coefficient valuesare resulting feedback coefficient values.
 13. The Galois fieldmultiplier method of claim 10 further comprising using multiple bits ofa multiplier as an index to said lookup table to generate one partialproduct term.
 14. The Galois field multiplier method of claim 10 furthercomprising using multiple bits of a feedback multiplier term as an indexto said lookup table to generate one feedback term.
 15. The Galois fieldmultiplier method of claim 10 wherein an irreducible polynomial isfixed.
 16. The Galois field multiplier method of claim 10 wherein anirreducible polynomial is programmable.
 17. A Galois field multipliersystem comprising: a means for multiplying terms; a means for addingterms; and a means for supplying one partial product value from multiplebits of a partial product multiplier.
 18. The Galois field multipliersystem of claim 17 wherein said means for supplying one partial productvalue includes a means for looking up said partial product value. 19.The Galois field multiplier system of claim 17 further comprising ameans for supplying one feedback value from multiple bits of a feedbackmultiplier.
 20. The Galois field multiplier system of claim 19 whereinsaid means for supplying one feedback value includes a means for lookingup said feedback value.
 21. A computer usable medium having a computerreadable program code embodied therein for causing a computer system toperform a finite field lookup table process comprising: creating afinite field lookup table; identifying a multiplier coefficient as anindex to said finite field lookup table; and utilizing an identifiedmultiplier coefficient to return a value from said finite field lookuptable.
 22. The computer usable medium of claim 21 wherein said finitefield lookup table is a partial product lookup table.
 23. The computerusable medium of claim 21 wherein said finite field lookup table is afeedback lookup table.
 24. The computer usable medium of claim 21wherein said finite field lookup table maps finite field lookup tablevalues with indexes associated with multiplier coefficients.
 25. Thecomputer usable medium of claim 21 further comprising: parsing a Galoisfield multiplication expression; and extracting coefficient values.